The present invention relates generally to clocked digital data processing systems. More particularly, the invention is directed to the generation of synchronized clock signals in data processing systems having multiple clock signals of different frequency.
The designs of computers and workstations continue to evolve at a rapid pace as new processors, interchangeably referred to herein as microprocessors or CPUs, become available and are integrated with input/output resources into more advanced versions of personal computers and workstations. The prevailing and evolutionary changes with computer models tend to be associated with the clock rates of the processors. Namely, it is very common for a fundamental design to be upgraded through the use of faster processors in half year or less increments of a model's life cycle. This has created a need for a versatile interface/bridge system, one which efficiently mates relatively low clock frequency input/output busses with high clock frequency processor busses, which processor busses are subject to evolutionary changes.
The presence of multiple busses operating at different frequencies within a common data processing system introduces a need for interface synchronization, so that clocked events on one bus, for example, the I/O bus, are synchronized to clocked events occurring on the processor bus. The clock signal synchronization problem is experienced by any circuit device which interacts at one time or another with both busses.
The synchronization becomes particularly relevant when one recognizes that the tolerances for the multiple clock signals may be materially different. For example, advanced computer designs will often operate the processor bus at a clock rate two or three times that of the I/O bus, while providing an I/O bus clock signal tolerance, in terms of the signal rise and fall skews, significantly larger than that allowed the processor clock. In part, this is attributable to the longer duration of the lower frequency I/O clock signals. Unfortunately, the extended skew tolerances exacerbate synchronization problems for devices operating with reference to both busses.
The synchronization problem becomes particularly acute when the interface/bridge device is an integrated circuit chip which receives the two clock signals as inputs and must derive from those two clock signals an internal clock suitable to synchronize with both busses. The prevailing design approach is to manage the clock signal tolerances internal to the integrated circuit by judiciously latching incoming signals. Unfortunately, that design approach becomes less viable as the frequencies increase, and lacks the flexibility needed with evolving designs in which the ratio of clock frequencies change.
What is needed is a design, and in particular an integrated circuit design, which can automatically determine the relative frequencies between harmonicly related clock signals, and based upon that determination select and generate a synthetic clock signal presenting an accurate synchronization of one of the clock signals to the selected other clock signal.